1. Field of the Invention
The present invention is related to chip stack structure, especially related to a chip stack structure using conductive film bridge adhesive technology.
2. Description of Related Art
Since a single chip cannot withstand the electrical current of an entire system, it is generally required to use two or more chips to overcome this problem, however, the substrate area will be have to be increased due to placing the chips horizontally. As shown in FIG. 1, an integrated power module has a plurality of separated chips 1 disposed on a single substrate 2, and then welding wires 3 are bonded to electrically connect the chips with each other. However, the overall size of the package increases because the chip 1 becomes more dense in this kind of structure.
With the advancement of technology, electronic products tend towards miniaturization and providing high performance to meet the needs of customers. In order to improve the performance and the capacity rate of a single package structure, three-dimensional (3D) package is widely adopted in the present day. Two or more chips 1 are stacked in a single package structure in order to provide a 3D package with compactly stacked and interconnected chips 1. As shown in FIG. 2, a conventional chip stack structure 4 is disposed with a plurality of chips, which are stacked up and down on a substrate 2. In the chip stack structure 4, a first chip 1a is adhered to the substrate 2 by an adhesive, and a plurality of first welding wires 3a are bonded and electrically connected to first pads 5a on the surface of the first chip 1a and contacts 6 on the substrate 2. Then, a second chip 1b is disposed on the first chip 1a. The adhesive 7 is applied between the first chip 1a and the second chip 1b in advance to adhere the second chip 1b to the first chip 1a and partially covers the first welding wires 3a. The thickness of the adhesive 7 exceeds the arc height of the first welding wires 3a in case of the first welding wires 3a make contact with the second chip 1b. After stacking the second chip 1b, a plurality of second welding wires 3b are bonded to and electrically connected to second pads 5b of the second chip 1b and the contacts 6 on the substrate 2. Both this chip stack structure 4 and the one recited above use wire bonding for electrical connection between chips so there isn't any effective heat dissipation structure between the chips 1a, 1b. When the heat can't be timely dissipated, the effectiveness of the chips will decrease due to the increase in temperature. Moreover, the adhesive 7 in this case is easily interfered with due to high temperatures and welding wires, and there will be voids gathered in the adhesive 7. Once the number of voids is reaches a critical capacity, the adhesive bond of the adhesive 7 will be greatly reduced, which leads to the chips 1a, 1b not being able to be stacked successfully.
To sum up the above, the conventional chip stack structure has the above drawbacks and needs to be improved.